The continuous demand for higher computational and electrical performance combined with reduced product dimensions leads to an increased usage of low-k dielectric materials which are of porous nature. These materials are very sensitive to mechanical forces and thermal influences which lead to crack forming and delamination. Already small separation induced surface defects on the edge of the chip can lead to product failure. This explains why the yield of mechanical separation processes is too low.

As in the case of memory wafer separation the laser cutting tool offers a solution. For dicing of microprocessor wafers a two step process is used. Low power grooving of surface layers allows to separate low-k material virtually damage free. Subsequently sufficient laser power is used to dice through the silicon substrate which can be up to several 100 µm thick