ASMPT is the inventor of multi beam semiconductor dicing. With this experience we have developed a V-DOE dicing technology which allows full cut dicing of Low-K (thin) Si wafers including DAF or FOW while achieving high die strength (450-500Mpa) with a good quality and low CoO. The V-DOE process allows customers to dice through the full stack of materials using a single process step. No complicated and costly process flows required such as with DBG or other Hybrid dicing technologies. The unique slider concept (wafer stepper concept) allows high accuracy and reproducibility.
Key Features:
- Ability to dice substrate material as well as DAF or FOW. Thickness ranging from 10um up to 200um.
- High position accuracy and repro (< ± 1um)
- Narrow dicing width (< 12um for 100um thickness)
- Small HAZ (< 2um for 100um thickness)
- High UPH (typically 50% faster than competition) due to system concept design focused on laser material processing:
- ultra short index time
- Dual cassette stations
- Dual coat and clean stations
Summary Key Points:
- Unique Multi beam technology
- Active focus control to compensate for wafer thickness variations
- Planar motion system & active mounts for vibration compensation provide extremely high speed & accuracy
- Remote control and diagnostics for on the spot process support and faster service support
- 2 individual cassette stations to eliminate machine idle time
- Priority wafer or wafer inspection port for maximum flexibility and control
- (Multiple) Integrated coating/cleaning stations to maximize dicing productivity & flexibility
- Automatic beam splitting exchange for multiple applications
- Pre-alignment and contour station to enable maximum productivity
- Multi-Project Wafer (MPW) and broken wafer dicing capability for tool flexibility & higher wafer yield
- Secs Gem compatible
- Intuitive Graphical User Interface
Applications:
- RFIC
- HB-LED
- Memory (NAND & DRAM)
- Power
- LCD drivers
- Micro processors