V-DOE Dicing for Thin Si wafers

ASMPT has developed a proprietary process with a unique V-DOE Multi beam process for dicing of thin silicon (<<100 µm) wafers with a low CoO while achieving a high die strength (typically >500 MPa).

This technology allows in a single process step to dice through the Low-K/metal/passivation top layers, Si substrate and DAF or FOW with a high quality and die strength without the need for additional process steps. Additional steps are needed for other separation technologies such as DBG, SDBG or plasma dicing.